module mod5ctrl
			(
			 clock, resetn,
			 DATA_IN,
			 DIPSWn,

			 ROW_SEL, RX, TX, S1, S2, S3, S4,
			 PHI1, PHI2, PHI3, PHI4, PHI5, RESET_SUM,
			 CLK_NS, EXTINPUT_SEL, 
			
			 CLK_CISn,
			 ENA_CNT, WR, ADV_TKNn, RESET_CNTn,
			 PCn, ENA_WL, DLn, MUX_SEL,
			
			 RAMP_LATCH, RAMP_DB,
			 POD_CLK, POD_DB,
			
			 extin_latch, sig_sel,
			 dac_out
			);

input			clock, resetn;
input	[9:0]	DATA_IN;
input	[3:0]	DIPSWn;

output			ROW_SEL;
output			RX, TX, S1, S2, S3, S4;
output			PHI1, PHI2, PHI3, PHI4, PHI5, RESET_SUM;
output			CLK_NS, EXTINPUT_SEL;

output			CLK_CISn;
output			ENA_CNT, WR, ADV_TKNn, RESET_CNTn;
output			PCn, ENA_WL, DLn, MUX_SEL;

output			RAMP_LATCH;
output	[13:0]	RAMP_DB;

output			POD_CLK;
output	[15:0]	POD_DB;

output			extin_latch, sig_sel;
output	[13:0]	dac_out;

wire			zero;
wire			branch, decabnz;
wire			ioset, loadacc;
wire			swait;
wire			ramp, rsram, rlta;
wire			int_tmr;
wire			load_pc, cnten_pc, sclr_pc;
wire			load_opc, load_opr;
wire			load_acc, cntdn_acc, sclr_acc;
wire			load_cntref, cnten_tmr, sclr_tmr;
wire			init_porta, load_porta;
wire	[11:0]	INITA;
wire			init_portb, load_portb;
wire	[15:0]	INITB;
wire			sel_portb;
wire	[5:0]	PBADDR;
wire	[11:0]	PORTA;
wire	[15:0]	PORTB;
wire 	[27:0]	rA;
wire 	[27:0]	rB;

wire	[3:0]	rDIPSW;
wire			sclr_rampcnt, cnten_rampcnt;
wire			load_podreg;
wire			LATCH_LTAOUTn, ADV_LTAOUTn;

wire	[13:0]	rst;
wire	[13:0]	sig;
wire 	[3:0]	mul_coeff;
wire 	[9:0] 	rB_temp_sec;
//wire    [13:0]  sig00, sig01, sig10, sig11;
/*
Definition of port A (PORTA) and port B (PORTB)
For MOD2CIAS FPGA

Revision	: 1.00
Date		: APR-05-2004
Author		: Kunil Choe
CIS Module	: MOD2CIAS

Port A (PORTA[11:0])
	PORTA[0]	RX
	PORTA[1]	TX
	PORTA[2]	S1
	PORTA[3]	S2
	PORTA[4]	S3
	PORTA[5]	EXTIN_LATCH
	PORTA[6]	PHI1
	PORTA[7]	PHI2
	PORTA[8]	PHI3
	PORTA[9]	PHI4
	PORTA[10]	PHI5
	PORTA[11]	RESET_SUM

Port B (PORTB[15:0])
	PORTB[0]	CLK_CISn
	PORTB[1]	RESET_CNTn
	PORTB[2]	ADV_LTAOUTn
	PORTB[3]	ENA_CNT
	PORTB[4]	RAMP_LATCH
	PORTB[5]	WR
	PORTB[6]	ADV_TKNn
	PORTB[7]	PCn
	PORTB[8]	ENA_WL
	PORTB[9]	DLn
	PORTB[10]	MUX_SEL
	PORTB[11]	sig_sel
	PORTB[12]	sclr_rampcnt
	PORTB[13]	cnten_rampcnt
	PORTB[14]	load_podreg
	PORTB[15]	POD_CLK
*/

assign		RX				= PORTA[0];
assign		TX				= PORTA[1];
assign		S1				= PORTA[2];
assign		S2				= PORTA[3];
assign		S3				= PORTA[4];

assign		S4				= S3;
assign		extin_latch		= PORTA[5];

assign		PHI1			= PORTA[6];
assign		PHI2			= PORTA[7];
assign		PHI3			= PORTA[8];
assign		PHI4			= PORTA[9];
assign		PHI5			= PORTA[10];
assign		RESET_SUM		= PORTA[11];

assign		CLK_CISn        = PORTB[0];
assign		RESET_CNTn		= PORTB[1];
assign		ADV_LTAOUTn     = PORTB[2];
assign		ENA_CNT         = PORTB[3];
assign		RAMP_LATCH      = PORTB[4];
assign		WR              = PORTB[5];
assign		ADV_TKNn        = PORTB[6];
assign		PCn             = PORTB[7];
assign		ENA_WL          = PORTB[8];
assign		DLn             = PORTB[9];
assign		MUX_SEL         = PORTB[10];

assign		sig_sel			= PORTB[11];

assign		sclr_rampcnt    = PORTB[12];
assign		cnten_rampcnt   = PORTB[13];
assign		load_podreg     = PORTB[14];
assign		POD_CLK         = PORTB[15];


assign		INITA			= 12'b0000_0000_0000;
assign		INITB			= 16'b0000_0110_1100_0111;
assign		rst				= 14'hEBF;  /* 2.2V       */
assign 		mul_coeff 		= 4'hB;     /* X 11 */
//assign 		sig00 			= 16'h2447;  /* 1.8V-1mV   */
//assign 		sig01 			= 16'h24A8;  /* 1.8V-10mV  */
//assign 		sig10 			= 16'h2656;  /* 1.8V-50mV  */
//assign 		sig11 			= 16'h2871;  /* 1.8V-100mV */

assign		ROW_SEL			= 1'b0;
assign		EXTINPUT_SEL	= rDIPSW[2];
assign		CLK_NS			= 1'b0 ;
//assign 		sig 			= (rDIPSW[1])? ((rDIPSW[0])? sig11:sig10 ):((rDIPSW[0])? sig01:sig00);

/*
module ctrlpath
		(
		clock, resetn,

		zero_a, zero_b,
		
		branch, decabnz,
		ioset, loada, loadb,
		swait,
		ramp, rsram, rlta,

		int_tmr,
		rDIPSW,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, init_portb, load_portb,
		sel_portb, PBADDR
		);

*/
ctrlpath	CTRLPATH1	(.clock(clock), .resetn(resetn),

						 .zero_a(zero_a), .zero_b(zero_b),

						 .branch(branch), .decabnz(decabnz), .decbbnz(decbbnz),
						 .ioset(ioset), .loada(loada), .loadb(loadb),
						 .swait(swait),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .int_tmr(int_tmr),
						 .rDIPSW(rDIPSW),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_a(load_a), .cntdn_a(cntdn_a), .sclr_a(sclr_a),
						 .load_b(load_b), .cntdn_b(cntdn_b), .sclr_b(sclr_b),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta),
						 .init_portb(init_portb), .load_portb(load_portb),
						 .sel_portb(sel_portb), .PBADDR(PBADDR));
/*
module datapath
		(
		clock, resetn,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, INITA,
		init_portb, load_portb, INITB,
		sel_portb, PBADDR,
		
		zero_a, zero_b,
		
		branch, decabnz, decbbnz,
		ioset, loada, loadb,
		swait,
		ramp, rsram, rlta,
		int_tmr,
		
		PORTA, PORTB
		);

*/
datapath	DATAPATH1	(.clock(clock), .resetn(resetn),

						 .load_pc(load_pc), .cnten_pc(cnten_pc), .sclr_pc(sclr_pc),
						 .load_opc(load_opc), .load_opr(load_opr),
						 .load_a(load_a), .cntdn_a(cntdn_a), .sclr_a(sclr_a),
						 .load_b(load_b), .cntdn_b(cntdn_b), .sclr_b(sclr_b),
						 .load_cntref(load_cntref), .cnten_tmr(cnten_tmr), .sclr_tmr(sclr_tmr),
						 .init_porta(init_porta), .load_porta(load_porta), .INITA(INITA),
						 .init_portb(init_portb), .load_portb(load_portb), .INITB(INITB),
						 .sel_portb(sel_portb), .PBADDR(PBADDR),
						
						 .zero_a(zero_a), .zero_b(zero_b),

						 .branch(branch), .decabnz(decabnz), .decbbnz(decbbnz),
						 .ioset(ioset), .loada(loada), .loadb(loadb),
						 .swait(swait),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta),
						 .int_tmr(int_tmr),

						 .PORTA(PORTA), .PORTB(PORTB),
						 .rA(rA),	,.rB(rB) );
/*
rampcnt		RAMPCNT1	(.clock(clock), .resetn(resetn),
						 .sclr(sclr_rampcnt), .cnten(cnten_rampcnt),
						 .Q(RAMP_DB));
*/

crampcnt 	CRAMPCNT1 	(.clock(clock), .resetn(resetn),
										.sclr(sclr_rampcnt), .cnten(cnten_rampcnt),
										.gain(4'b1000), .offset(14'h1FFF ), .satlevel(10'h10),
										.Q(RAMP_DB)); 
// offset=14'h39F3=decimal 14835 =1.2V//

podreg		PODREG1		(.clock(clock), .resetn(resetn), .load(load_podreg),
						 .DATA({6'b0, DATA_IN}),
						 .Q(POD_DB));

dipswreg	DIPSWREG1	(.clock(clock), .resetn(resetn),
						 .DATAn(DIPSWn), .Q(rDIPSW));

/* 
module 		sig_mult 	(
 	sum,
	dataa,
	datab,
	result);
*/
sig_sub		SIG_SUB1 	(
						 .dataa ( 10'h65 ),
						 .datab ( rB[9:0] ),
						 .result ( rB_temp_sec )
						);


sig_mult 	SIG_MULT1 	(.sum(rst), .dataa(rB_temp_sec), .datab(mul_coeff), .result(sig));

/*
module extin_ctrl
			(
			 clock, resetn,
			 rst, sig,
			 sig_sel,
			 dac_out
			);
*/
extin_ctrl  EXTIN_CTRL1 (.clock(clock), .resetn(resetn),.rst(rst),.sig(sig),
                         .sig_sel(sig_sel), .dac_out(dac_out));

endmodule
